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<A name="Mrp"></A>                         Lattice Mapping Report File
Design:  awg
Family:  iCE40UP
Device:  iCE40UP5K
Package: SG48
Performance Grade:  High-Performance_1.2V

Mapper:    version Radiant Software (64-bit) 2022.1.0.52.3
Mapped on: Thu Mar 16 11:17:31 2023


<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>

Command line:   map -i awg_fpga_impl_1_syn.udb -pdc
     C:/Users/zyx/my_designs/awg_fpga/source/impl_1/awg.pdc -o
     awg_fpga_impl_1_map.udb -mp awg_fpga_impl_1.mrp -hierrpt -gui

<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
   Number of slice registers: 201 out of  5280 (4%)
   Number of I/O registers:      0 out of   117 (0%)
   Number of LUT4s:           454 out of  5280 (9%)
      Number of logic LUT4s:             131
      Number of inserted feedthru LUT4s:  97
      Number of ripple logic:            113 (226 LUT4s)
   Number of IO sites used:   16 out of 39 (41%)
      Number of IO sites used for general PIO: 16
      Number of IO sites used for I3C: 0 out of 2 (0%)
      (note: If I3C is not used, its site can be used as general PIO)
      Number of IO sites used for PIO+I3C: 16 out of 36 (44%)
      Number of IO sites used for OD+RGB IO buffers: 0 out of 3 (0%)
      (note: If RGB LED drivers are not used, sites can be used as OD outputs,
       see TN1288 iCE40 LED Driver Usage Guide)
      Number of IO sites used for PIO+I3C+OD+RGB: 16 out of 39 (41%)
   Number of DSPs:             5 out of 8 (62%)
   Number of I2Cs:             0 out of 2 (0%)
   Number of High Speed OSCs:  0 out of 1 (0%)
   Number of Low Speed OSCs:   0 out of 1 (0%)
   Number of RGB PWM:          0 out of 1 (0%)
   Number of RGB Drivers:      0 out of 1 (0%)
   Number of SCL FILTERs:      0 out of 2 (0%)
   Number of SRAMs:            0 out of 4 (0%)
   Number of WARMBOOTs:        0 out of 1 (0%)
   Number of SPIs:             0 out of 2 (0%)
   Number of EBRs:             10 out of 30 (33%)
   Number of PLLs:             0 out of 1 (0%)
   Number of Clocks:  1
      Net clk_c: 193 loads, 193 rising, 0 falling (Driver: Port clk)
   Number of Clock Enables:  16
      Net VCC_net: 30 loads, 0 SLICEs
      Net U1.n2621: 8 loads, 8 SLICEs
      Net U1.rxd_data_7__N_70: 8 loads, 8 SLICEs
      Net U1.n2744: 8 loads, 8 SLICEs
      Net U1.n2745: 8 loads, 8 SLICEs
      Net U1.n728: 3 loads, 3 SLICEs
      Net U1.n2628: 8 loads, 8 SLICEs
      Net U1.n2751: 1 loads, 1 SLICEs
      Net U1.n3856: 1 loads, 1 SLICEs
      Net U1.n2733: 1 loads, 1 SLICEs
      Net U1.n3860: 1 loads, 1 SLICEs

      Net U1.n3851: 1 loads, 1 SLICEs
      Net U1.n4030: 1 loads, 1 SLICEs
      Net U1.n3864: 1 loads, 1 SLICEs
      Net U1.n3853: 1 loads, 1 SLICEs
      Net U1.n2752: 8 loads, 8 SLICEs
   Number of LSRs:  1
      Net rst_n_N_209: 144 loads, 144 SLICEs
   Top 10 highest fanout non-clock nets:
      Net rst_n_N_209: 144 loads
      Net VCC_net: 64 loads
      Net rst_n_c: 31 loads
      Net U3.n2233: 20 loads
      Net U3.addr[0]: 18 loads
      Net U3.addr[1]: 18 loads
      Net U3.addr[5]: 18 loads
      Net U3.addr[6]: 18 loads
      Net U3.addr[7]: 18 loads
      Net U3.addr[8]: 18 loads




   Number of warnings:  0
   Number of errors:    0




<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>

   No errors or warnings present.



<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>

+---------------------+-----------+-----------+-------+-------+-----------+
| IO Name             | Direction | Levelmode |  IO   |  IO   | Special   |
|                     |           |  IO_TYPE  |  REG  |  DDR  | IO Buffer |
+---------------------+-----------+-----------+-------+-------+-----------+
| f_mosi              | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| f_sck               | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| CS_N                | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| rst_n               | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| clk                 | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| dac_sclk            | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| dac_data[0]         | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| dac_data[1]         | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| dac_data[2]         | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| dac_data[3]         | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+

| dac_data[4]         | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| dac_data[5]         | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| dac_data[6]         | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| dac_data[7]         | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| dac_data[8]         | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| dac_data[9]         | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+



<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>

Block i1 was optimized away.



<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
---------------

Instance Name: U3/mult_792
         Type: DSP
Instance Name: U3/mult_416
         Type: DSP
Instance Name: U3/mult_386
         Type: DSP
Instance Name: U3/mult_415
         Type: DSP
Instance Name: U3/mux_264
         Type: EBR
Instance Name: U3/mult_791
         Type: DSP
Instance Name: U3/inst_sin_rom/lscc_rom_inst/u_rom/PRIM_MODE.xADDR[0].xDATA[2].m
     em_file.mem0/iCE40UP.sp4k
         Type: EBR
Instance Name: U3/inst_sin_rom/lscc_rom_inst/u_rom/PRIM_MODE.xADDR[0].xDATA[1].m
     em_file.mem0/iCE40UP.sp4k
         Type: EBR
Instance Name: U3/inst_sin_rom/lscc_rom_inst/u_rom/PRIM_MODE.xADDR[0].xDATA[0].m
     em_file.mem0/iCE40UP.sp4k
         Type: EBR
Instance Name: U3/inst_sanjiao_rom/lscc_rom_inst/u_rom/PRIM_MODE.xADDR[0].xDATA[
     2].mem_file.mem0/iCE40UP.sp4k
         Type: EBR
Instance Name: U3/inst_sanjiao_rom/lscc_rom_inst/u_rom/PRIM_MODE.xADDR[0].xDATA[
     1].mem_file.mem0/iCE40UP.sp4k
         Type: EBR
Instance Name: U3/inst_sanjiao_rom/lscc_rom_inst/u_rom/PRIM_MODE.xADDR[0].xDATA[
     0].mem_file.mem0/iCE40UP.sp4k
         Type: EBR
Instance Name: U3/inst_fangbo_rom/lscc_rom_inst/u_rom/PRIM_MODE.xADDR[0].xDATA[2
     ].mem_file.mem0/iCE40UP.sp4k
         Type: EBR
Instance Name: U3/inst_fangbo_rom/lscc_rom_inst/u_rom/PRIM_MODE.xADDR[0].xDATA[1
     ].mem_file.mem0/iCE40UP.sp4k
         Type: EBR

Instance Name: U3/inst_fangbo_rom/lscc_rom_inst/u_rom/PRIM_MODE.xADDR[0].xDATA[0
     ].mem_file.mem0/iCE40UP.sp4k
         Type: EBR



<A name="mrp_consum"></A><B><U><big>Constraint Summary</big></U></B>
------------------

   Total number of constraints: 16
   Total number of constraints dropped: 0



<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
-------------------------

   Total CPU Time: 0 secs
   Total REAL Time: 0 secs
   Peak Memory Usage: 63 MB












































Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995
     AT&amp;T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent
     Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems
     All rights reserved.
Copyright (c) 2002-2022 Lattice Semiconductor
     Corporation,  All rights reserved.



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</PRE></DIV>

<DIV id="toc" class="radiant"><span onmousemove="showTocList()">Contents</span>
<UL id="toc_list">
<LI><A href=#mrp_di>Design Information</A></LI>
<LI><A href=#mrp_ds>Design Summary</A></LI>
<LI><A href=#mrp_dwe>Design Errors/Warnings</A></LI>
<LI><A href=#mrp_ioa>IO (PIO) Attributes</A></LI>
<LI><A href=#mrp_rm>Removed logic</A></LI>
<LI><A href=#mrp_asic>ASIC Components</A></LI>
<LI><A href=#mrp_consum>Constraint Summary</A></LI>
<LI><A href=#mrp_runtime>Run Time and Memory Usage</A></LI>
</UL>
</DIV>

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